In the design of synchronous digital circuits, clock signals are used to synchronize computations in the digital circuits. The task of the clock signals is to ensure that all storage elements update their values simultaneously. Storage elements, such as latches and flip-flops, are responsive to a transition of a clock signal input to: sample output digital signals of combinational logic; internally preserve the digital values as the state of the circuit; and make the state available for new combinational logic computations after a certain delay has elapsed since the clock signal transition.
A storage element makes its internal digital state available by driving its output signal to a corresponding voltage level. When the new voltage level is higher than the previous one, current is briefly drawn from the voltage supply to charge the signal capacitance. Conversely, current is briefly dumped into the ground network when the new voltage level is lower than the previous one.
Conventional schemes for distributing clock signals to storage elements concentrate on ensuring a high degree of synchronism among all clock signals. Clocks are typically distributed in a tree-like structure, whereby delays in different branches can be balanced to a high degree. One benefit is that the clock rate can be high, because it is not limited by variations in clock arrival times. Even for lower clock rates, uniformity brings predictability and therefore simplifies the overall design problem.
Highly balanced clock distribution networks cause the outputs of all storage elements in the design to toggle virtually simultaneously. The capacitive loads driven by the flip-flop outputs are then charged simultaneously, briefly drawing a large aggregate current spike from the supply. Such current spikes are undesirable for several reasons.
Metal migration in supply wires is a major reliability problem. The rate of migration depends strongly on the maximum current density which occurs in the wire. Large current spikes thus disadvantageously require wider supply wires with the concomitant cost in area.
Large current spikes feature large values of dI/dt. Together with the parasitic inductance present in the IC package, the current spikes thus cause voltage fluctuations on the supply lines. These fluctuations can cause both malfunction of the digital circuits and reduced performance levels in co-located analog circuitry. These problems can be addressed with advanced packaging and on-chip decoupling capacitance, both of which disadvantageously increase cost.
Also, large current spikes can themselves couple inductively into other parts of the design and cause malfunction or performance reduction.
The present invention mitigates supply current spikes caused by simultaneous toggling of storage element output signals. This can be achieved by using storage elements which differ in their respective clock-to-output delays. The delay variation among storage elements is also referred to herein as "delay spread". The delay spread causes the outputs of different storage elements to toggle at slightly different times, such that the individual current spikes of the respective storage elements are slightly staggered (i.e., offset from one another) in time. The delay spread therefore serves to "smear out" the overall (aggregate) current spike over time, advantageously reducing its maximum value as well as the maximum value of dI/dt.